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XCR3064XL 64 Macrocell CPLD
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DS017 (v1.1) August 30, 2000
Preliminary Product Specification
Features
* * * * 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages * * * * * * * * 44-pin VQFP (36 user I/O pins) 48-ball CS BGA (40 user I/O pins) 56-ball CP BGA (48 user I/O pins) 100-pin TQFP (68 user I/O pins) Ultra-low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five metal layer reprogrammable process FZPTM CMOS design technology In-system programming Input registers Predictable timing model Up to 23 available clocks per logic block Excellent pin retention during design changes Full IEEE Standard 1149.1 boundary-scan (JTAG) Four global clocks Eight product term control terms per logic block
Description
The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four logic blocks provide 1,500 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz.
TotalCMOSTM Design Technique for Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3064XL TotalCMOS CPLD (data taken with four up/down, loadable 16-bit counters at 3.3V, 25C).
Optimized for 3.3V systems
Advanced system features
Fast ISP programming times Port Enable pin for dual function of JTAG ISP pins 2.7V to 3.6V industrial temperature range Programmable slew rate control per macrocell Security bit prevents unauthorized access Refer to XPLA3 family data sheet (DS012) for architecture description
(c) 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS017 (v1.1) August 30, 2000 Preliminary Product Specification
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XCR3064XL 64 Macrocell CPLD
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35.0 30.0 25.0
Typical ICC (mA)
20.0 15.0 10.0 5.0 0.0 0 20 40 60 80 100 120 140
Frequency (MHz)
DS017_01_082800
Figure 1: ICC vs. Frequency at VCC = 3.3V, 25C Table 1: ICC vs. Frequency (VCC = 3.3V, 25C) Frequency (MHz) Typical ICC (mA) 0 0 1 0.2 5 1.0 10 2.0 20 3.9 40 7.6 60 11.3 80 14.8 100 18.5 120 22.1 140 25.6
DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol VOH VOL IIL IIH ICCSB ICC Parameter Output High voltage for 3.3V outputs Output Low voltage for 3.3V outputs Input leakage current I/O High-Z leakage current Standby current Dynamic current(2,3) Test Conditions IOH = -8 mA IOL = 8 mA VIN = GND or VCC VIN = GND or VCC VCC = 3.6V f = 1 MHz f = 50 MHz CIN CCLK CI/O Input pin capacitance(4) Clock input capacitance(4) I/O pin capacitance (4) f = 1 MHz f = 1 MHz f = 1 MHz Min. 2.4 -10 -10 Max. 0.4 10 10 100 0.5 15 8 12 10 Unit V V A A A mA mA pF pF pF
Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See Table 1, Figure1 for typical values. 3. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing. 4. Typical values not tested.
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DS017 (v1.1) August 30, 2000 Preliminary Product Specification
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XCR3064XL 64 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-6 Symbol TPD1 TPD2 TCO TSUF TSU TH TWLH TtPLH TR TL fSYSTEM TCONFIG TPOE TPOD TPCO TPAO Parameter Propagation delay time (single p-term) Propagation delay time (OR array)(3) Clock to output (global synchronous pin clock) Setup time fast Setup time Hold time Global Clock pulse width (High or Low) P-term clock pulse width Input rise time Input fall time Maximum system frequency Configuration time(4) disabled(5) P-term OE to output enabled P-term OE to output P-term clock to output P-term set/reset to output valid Min. 2.0 4.0 0 2.5 4.0 Max. 5.5 6.0 4.0 20 20 145 20.0 7.5 7.5 6.5 8.0 2.5 4.8 0 3.0 5.0 Min. -7 Max. 7.0 7.5 5.0 20 20 119 20.0 9.3 9.3 8.3 9.3 Min. 3.0 6.3 0 4.0 6.0 -10 Max. 9.1 10.0 6.5 20 20 95 20.0 11.2 11.2 10.7 11.2 Unit ns ns ns ns ns ns ns ns ns ns MHz s ns ns ns ns
Notes: 1. Specifications measured with one output switching. 2. See XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. Typical current draw during configuration is 8 mA at 3.6V. 5. Output CL = 5 pF.
DS017 (v1.1) August 30, 2000 Preliminary Product Specification
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Timing Model
The XPLA3 architecture follows a simple timing model that allows deterministic timing in design and redesign. The basic timing model is shown in Figure 2. One key feature of the XPLA3 CPLD is the ability to have up to 48 product term inputs into a single macrocell and maintain consistent timing. This is achieved through the use of a fully populated PLA (Programmable AND Programmable OR Array) which also has the ability to share product terms and only use the required amount of product terms per macrocell. There is a fast path (TLOGI1) into the macrocell which is used if there is a single product term. The TLOGI2 path is used for multiple product term timing. For optimization of logic, the XPLA3 CPLD architecture includes a Fold-back NAND path (TLOGI3). There is a fast input path to each macrocell if used as an Input Register (TFIN). XPLA3 also includes universal control terms (TUDA) that can be used for synchronization of the macrocell registers in different logic blocks. There is also slew rate control and output enable control on a per macrocell basis.
TF
TIN
TLOGI1,2
DLT CE
Q
TOUT TEN TSLEW
TFIN
TGCK
TLOGI3
TUDA
S/R
DS017_02_042800
Figure 2: XPLA3 Timing Model
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DS017 (v1.1) August 30, 2000 Preliminary Product Specification
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XCR3064XL 64 Macrocell CPLD
Internal Timing Parameters
-6 Symbol Buffer Delays TIN TFIN TGCK TOUT TEN Input buffer delay Fast Input buffer delay Global Clock buffer delay Output buffer delay Output buffer enable/disable delay 1.3 1.8 0.8 2.2 4.2 1.6 2.5 1.0 2.7 5.0 2.2 3.1 1.3 3.6 5.7 ns ns ns ns ns Parameter Min. Max. Min. -7 Max. Min. -10 Max. Unit
Internal Register and Combinatorial Delays TLDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI1 TLOGI2 Latch transparent delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output delay Register async. S/R to output delay Register async. recovery Internal logic delay (single p-term) Internal logic delay (PLA OR term) 1.0 4.0 2.0 3.0 1.3 1.0 2.5 4.0 2.0 2.5 1.0 5.5 2.5 4.5 1.6 1.3 2.3 5.0 2.7 3.2 1.2 6.7 3.0 5.5 2.0 1.6 2.1 6.0 3.3 4.2 ns ns ns ns ns ns ns ns ns
Feedback Delays TF ZIA delay 2.4 2.9 3.5 ns
Time Adders TLOGI3 TUDA TSLEW Fold-back NAND delay Universal delay Slew rate limited delay 6.0 1.5 4.0 7.5 2.0 5.0 9.5 2.5 6.0 ns ns ns
DS017 (v1.1) August 30, 2000 Preliminary Product Specification
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Switching Characteristics
VCC
S1 Component R1 R2 C1 VOUT R2 C1 Values 390 390 35 pF
R1 VIN
Measurement TPOE (High) TPOE (Low) TP
S1 Open Closed Closed
S2 Closed Open Closed
Note: For TPOD, C1 = 5 pF S2
DS017_03_050200
Figure 3: AC Load Circuit
5.6 5.5 5.4
+3.0V 90%
10% 0V
(ns)
5.3 5.2
TR
1.5 ns
TL
1.5 ns
5.1 5.0 4.9 1 2 4 8 16
Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
DS017_05_042800
Number of Adjacent Outputs Switching
DS017_04_042800
Figure 5: Voltage Waveform
Figure 4: Derating Curve for TPD2
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DS017 (v1.1) August 30, 2000 Preliminary Product Specification
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XCR3064XL 64 Macrocell CPLD Table 2: XCR3064XL Pin Descriptions (Continued) Function Block Macrocell CP56 C8 A8 A9 A5 A10 B10 C10(1) D8 E8 F8 E10 C4 C3 A1 B1 A2 A3 C1(1) D1 D3 E3 F1 F10(1) VQ100 85 84 83 81 80 79 76 75 73(1) 71 69 68 67 65 64 63 92 93 94 96 97 98 99 100 4(1) 6 8 9 10 12 13 14 62(1) C C C C C C C C C C C C C C C D D D D D D D D D D D D D D D D
Notes: 1. JTAG pins
Pin Descriptions
Table 2: XCR3064XL Pin Descriptions Function Block Macrocell A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 VQ44 35 34 33 32(1) 31 30 28 27 42 43 44 1(1) 2 3 5 6 26(1) CS48 C5 A6 A7 B6 B7(1) D4 C6 D6 D7 A2 A1 C4 B2 B1(1) C2 C1 D3 D1 E5(1)
VQ44 25 23 22 21 20 19 18 40(1) 8 10 11 12 13 14 15 -
CS48 E7 F7 F6 G7 G6 F5 G5 F4 D2(1) E1 F1 G1 E4 F2 G2 F3 G3 -
CP56 G8 H10 K8 K10 K9 J10 H8 H7 H6 K7 G1(1) F3 G3 J1 K1 K4 K2 K3 H3 H4 K5 -
VQ100 61 60 58 57 56 54 52 48 47 46 45 44 42 41 40 15(1) 16 17 19 20 21 23 25 29 30 31 32 33 35 36 37
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DS017 (v1.1) August 30, 2000 Preliminary Product Specification
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XCR3064XL 64 Macrocell CPLD Table 3: X36CR3064XL Global, JTAG, Port Enable, Power, and No connect Pins Pin Type IN0 / CLK0 IN1 / CLK1 IN2 / CLK2 IN3 / CLK3 TCK TDI TDO TMS PORT_EN VCC GND No Connects VQ44 40 39 38 37 26 1 32 7 4(1) 9, 17, 29, 41 16, 24, 36 CS48 A3 B4 A4 B5 E5 B1 B7 D2 C3(1) B3, C7, E2, G4 A5, E3, E6 CP56 C5 C6 C7 A6 F10 C1 C10 G1 E1(1) A4, D10, H1, H5 A7, G10, K6 VQ100 90 89 88 87 62 4 73 15 11(1) 3, 18, 34, 39, 51, 66, 82, 91 26, 38, 43, 59, 74, 86, 95 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78
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Notes: 1. Port Enable is brought Low to enable JTAG pins when JTAG pins are used as I/O. See family data sheet for more information.
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DS017 (v1.1) August 30, 2000 Preliminary Product Specification
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XCR3064XL 64 Macrocell CPLD
Ordering Information
Example: XCR3064XL -7 VQ 44 C
Device Type Speed Grade Temperature Range Number of Pins Package Type Speed Options -10: 10 ns pin-to-pin delay -7: 7.5 ns pin-to-pin delay -6: 6.0 ns pin-to-pin delay Temperature Range C = Commercial TA = 0C to +70C I = Industrial TA = -40C to +85C Packaging Options VQ100: 100-pin Very Thin Quad Flat Package VQ44: 44-pin Very Thin Quad Flat Package CS48: 48-ball Chip Scale Package CP56: 56-ball Chip Scale Package
Component Availability
Pins Type Code XCR3064XL -6 -7, -10 100 Plastic VQFP TQ100 C C,I 56 Plastic BGA CP56 C C,I 48 Plastic BGA CS48 C C,I 44 Plastic VQFP VQ44 C C,I
Revision History
The following table shows the revision history for this document.. Date 06/01/00 08/30/00 Version 1.0 1.1 Initial Xilinx release. Added 48-ball CS BGA package. Revision
DS017 (v1.1) August 30, 2000 Preliminary Product Specification
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